It is known in the prior art to include on integrated circuit components of high-performance computer systems, one or more registers configured to record data associated with various events or operations occurring within the device. Such registers may record the number of times an event occurs. In some cases, such registers may record the time (e.g., number of clocks) for which a specified condition is true.
The data recorded in such registers may be useful in monitoring the performance of a processor or other components of the high-performance computer system, or of a program executing on a processor. As such, the processor may periodically read the data from such registers, and analyze the data to assess system hardware or software performance. To that end, the registers must be coupled to the processor via, one or more communications lines, such via dedicated communications lines, or via a data bus.
Both the registers and the communications lines impose a hardware cost on the component integrated circuit. For example, the registers are typically composed of Hip-flops, and must be large enough to store the maximum possible value of data recorded during an acquisition period. Such registers are physically large, and in the aggregate may also consume significant amounts of power. For example, some high-performance computer systems may have hundreds of registers, or even one thousand or more such registers, disposed across a given integrate circuit component.